Performance and ASIC Designs of the K-best LSD and LMMSE Detectors for LTE Downlink
We consider performance comparison and application specific integrated circuit (ASIC) designs of linear minimum mean-square error (LMMSE) and K-best list sphere detector (LSD) algorithms for 4 × 4 and 8 × 8 multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. Requirements for higher data rate and lower power consumption set new challenges for implementation. In order to minimize the power consumption, an optimal detector would be able to switch the detection algorithm to suit the channel conditions. The detectors are designed for three different modulation schemes using 28 nm complementary metal oxide semiconductor (CMOS) technology. The communications performance is evaluated in the Third Generation Partnership Project (3GPP) Long-Term Evolution (LTE) system. The impact of transmit precoding is considered. The ASIC designs aim at providing the hardware design aspects to the comparison of detectors. The designs are synthesized and complexity and power consumption results are found. Based on the ASIC synthesis and communications performance results, we show the performance–energy efficiency and performance–complexity comparison. We also present the most suitable scenarios for a low-power detector and show how the transmit precoding impacts the detector selection.