Two-Stage Internal DAC Mismatch Mitigation for a Continuous-Time Delta-Sigma ADC

For continuous-time multi-bit Delta-Sigma data converters, mitigating the dynamic mismatch of the multi-bit digital-to-analog converter (DAC) with the so-called ISI-shaping DAC-encoder is a currently active research topic. ISI-shaper linearizes both static and dynamic DAC mismatch via spectral shaping of mismatch noise. However, such encoder may be too timing-, area-or power-critical for Delta-Sigma analog-to-digital converters. This paper proposes a novel approach viable for Delta-Sigma analog-to-digital data conversion. Here, the static portion of the DAC mismatch is linearized in the DAC feedback and the dynamic portion will be linearized digitally. Measuring and storing the ISI-error digitally requires error calibration for which this paper suggests an online approach. The proposed digital ISI-error correction can be used for both one-and multi-bit data converters.