Modeling and Physical Insights Into Negative Bias Temperature Instability in CFETs

This work presents a comprehensive simulation-based study of negative bias temperatureinstability (NBTI) in p-type complementary FETs (p-CFETs) employing a hybrid modeling framework that integrates multistate configuration, activated barrier double well thermionic (ABDWT), and transient trap occupancy models (TTOMs) within Sentaurus TCAD. Emphasis is placed on hydrogen-related degradation mechanisms, including species transport, trap depassivation, andcharge trapping kinetics at both the channel/SiO2 and SiO2/HfO2 interfaces. The model captures the evolution of interface charge and trap occupancy as functions of gate stress voltage (Vgstr), temperature (T), and stress time (tstr). Simulated results reveal that hydrogen diffusion andtrapping dynamics lead to spatially extended degradation, not limited to the immediate channel interface. The framework provides spatially resolved insight into reliability-limiting mechanisms in advanced 3-D CMOS platforms. © 1963-2012 IEEE.