Ka-band stacked power amplifier on 22 nm CMOS FDSOI technology utilizing back-gate bias for linearity improvement

This paper presents a method for extending millimeter wave power amplifier (PA) linear range by fine tuning the CMOS SOI device output characteristics via back-gate biasing. The effect of back-gate biasing to PA performance is measured and reported. It is demonstrated how implementing the same bias point with different back-gate values affects the linear range of the fabricated PA. By applying positive back-bias to the NFET devices, the measured PA displays minimum AM-PM and reaches maximum output power, PAE and 1 dB compression point of 16.3 dBm, 23 % and 13.9 dBm, respectively. EVM of 6.8 % and ACLR of −29.3 dBC were achieved at 5 dBm average output channel power with a 100MHz 64-QAM OFDM signal.

Authors

Rusanen Jere, Hietanen Mikko, Sethi Alok, Rahkonen Timo, Pärssinen Aarno, Aikio Janne P.

Publication type

A4 Article in conference proceedings

Place of publication

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Published

Full citation

J. Rusanen, M. Hietanen, A. Sethi, T. Rahkonen, A. Pärssinen and J. P. Aikio, "Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity Improvement," 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, 2019, pp. 1-4. doi: 10.1109/NORCHIP.2019.8906915

DOI

https://doi.org/10.1109/NORCHIP.2019.8906915

Read the publication here

http://urn.fi/urn:nbn:fi-fe2019121748458