Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers
This paper discusses the design requirements of class C auxiliary (aux) amplifiers deployed in Doherty power amplifiers (DPA). Taking conduction angle and back-off (BO) level into account a global design chart is presented which can be utilized to properly dimension the aux amplifier. Based on the proposed method a class C power amplifier is designed and exploited in a DPA circuit at 28GHz which is evaluated using simulations based on 45nm CMOS technology. Simulations reveal 27dBm saturated output power, 60% maximum drain efficiency (DE), 45% DE at 6dB BO, and 2 times efficiency enhancement at 6dB BO which is a new record in this trend.